1. Field of the Invention
This invention relates to integrated circuits and, more particularly, to cell based integrated circuit architecture that is configurable for the formation of logic devices and/or single/dual port memory devices.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
An integrated circuit generally includes the interconnection of various circuit elements. Those circuit elements include transistors, resistors, capacitors, logic gates, flip-flops, registers, etc. In order to achieve functionality, the various circuit elements must be interconnected with attention given to where those elements are relative to each other. In particular, performance of an integrated circuit is affected by where the elements are connected and the interconnect length between elements. As such, optimal performance of circuit elements is generally dictated by the “layout” of the integrated circuit. Often, however, a tradeoff between performance and cost exists for layout considerations. For example, in an application-specific integrated circuit (ASIC), placement of elements and the interconnection therebetween is unique to that particular integrated circuit design. That is, layout is performed on a chip-by-chip basis and cannot be easily modified whenever a design change is needed for that particular product. An ASIC thereby enjoys the benefits of high performance, but also has a fairly high non-recurring expense each time a design change is needed.
At the opposite end of the spectrum from ASIC designs is the more versatile gate array concept. A typical gate array consists of pre-designed circuit units or cells that are wired together to rapidly implement the final integrated circuit customer-specific functionality. The pre-designed circuit elements are called basic cells that, when interconnected, becomes the macro cell building blocks for the final integrated circuit product. The functionality of the final integrated circuit is thereby dictated by the interconnection of the macro cells. Gate array technology allows the pre-designed circuit unit to be fixed and need not change from one final circuit design to the next. In this manner, the design change can be implemented on the variable fabrication layers, yet the fixed layers will remain the same. Placement of interconnection that can vary depending on the intended circuit design adds configurability (or reconfigurability) to the gate array design. Thus, the concept of “fixed” and “variable” cell design of gate array technology offers a lower non-recurring expense if any design change is needed. Gate array technology generally allows changes to be made in the field to implement what is known as field-programmable gate arrays (FPGAs). FPGAs unfortunately have lower performance and higher power consumption relative to ASIC designs.
A special form of ASIC, known as structured or platform ASIC, serves somewhat as a compromise between FPGAs and standard ASICs. Similar to gate arrays, structured ASICs implement basic cells that are interconnected to form circuit elements. However, structured ASICs are not programmed in the field as in FPGAs, nor do structured ASICs consist of pre-designed circuit elements (e.g., logic gates, flip-flops, registers, etc.) that are wired together to form the integrated circuit. Instead, structured ASIC technology utilizes cells having a fixed pattern of transistors that are configurable for forming circuit elements with overlying variable interconnect layers. While structured ASICs have better performance and lower power consumption than gate arrays and have a lower non-recurring expense relative to standard ASICs, structured ASICs nonetheless have limitations as to what type of integrated circuit they can form. In particular, conventional structured ASICs are generally limited to forming logic circuits, such as NAND gates, NOR gates, etc. However, with the advent of greater integration and the use of system-on-chip (SoC) technology, modern designs mandate that the final integrated circuit contain more than just logic gates.
It would be desirable to implement a structured ASIC that can be reconfigured as logic gates, registers, flip-flops, and all other logic circuitry, as well as or in addition to memory. It would also be desirable to introduce a structured ASIC that can achieve a single port or dual port memory cell occupying a minimal amount of substrate space.